VeriFlow-CC

Dependencies

• Python 3.10+ (for state.py, no pip packages)
• Claude Code (logged in)
• iverilog / vvp (optional, for lint/sim stages)
• yosys (optional, for synth stage)

No pip install required.

1. Install from Source

git clone https://github.com/bjwanneng/veriflow-cc.git
cd veriflow-cc
python install.py

Installs to ~/.claude/: - skills/vf-rtl/SKILL.md — Pipeline orchestration skill - skills/vf-rtl/core/state.py — State management - skills/vf-rtl/analysis/vcd2table.py — VCD waveform analysis - skills/vf-rtl/coding_style.md — Verilog coding style rules - skills/vf-rtl/runners/cocotb_runner.py — Cocotb simulation runner - skills/vf-rtl/runners/iverilog_runner.py — Pure-Verilog simulation runner - skills/vf-rtl/analysis/timing_contract_checker.py — Timing contract validator - skills/vf-rtl/runners/benchmark_runner.py — Batch evaluation & reporting - skills/vf-rtl/analysis/bug_pattern_match.py — Automated divergence pattern matching - skills/vf-rtl/analysis/corner_case_generator.py — Boundary test vector generation - skills/vf-rtl/analysis/design_graph.py — Module connectivity graph analysis - skills/vf-rtl/kb/knowledge_base.py — Cross-project bug pattern learning - skills/vf-rtl/kb/reference_kb.py — Type-matched reference RTL retrieval (for vf-coder) - skills/vf-rtl/verify/synth_score.py — Synthesis-quality scoring from yosys reports - skills/vf-rtl/verify/candidate_selector.py — Multi-candidate RTL selection (test-time scaling) - skills/vf-rtl/analysis/coverage_analyzer.py — Functional coverage scoring (coverage-driven verification) - skills/vf-rtl/verify/formal_prove.py — Generate + prove Verilog formal properties via SymbiYosys - skills/vf-rtl/kb/self_improve.py — Cross-run self-improvement loop (benchmark-gated, reversible) - agents/vf-coder.md — RTL code generation sub-agent - agents/vf-spec-golden.md — Spec + golden model generation sub-agent - agents/vf-tb-gen.md — Testbench generation sub-agent - agents/vf-linter.md — Lint sub-agent - agents/vf-synthesizer.md — Synthesis sub-agent

Uninstall: python install.py --uninstall

Uninstall

python install.py --uninstall

Quick Start

Persistent EDA Environment

EDA tool paths (iverilog, vvp, yosys) are discovered once in Step 0 and saved to .veriflow/eda_env.sh. Every subsequent EDA command sources this file, avoiding the "PATH doesn't persist between Bash calls" issue. eda_env.sh also exports PYTHONPATH pointing at the installed skill directory, so helper scripts can import state.py without per-call PYTHONPATH prefixes.

Interface Lock

spec.json port definitions are locked after Stage 1. Port semantic fields enforce consistent interpretation across all stages: - reset_polarity: "active_high" only (reset ports must declare this) - handshake: "hold_until_ack" | "single_cycle" | "pulse" (valid ports must declare this) - ack_port: name of the associated ack input (required for hold_until_ack)

Pipeline Stages

Strict sequential execution, no skipping:

spec_golden → codegen → verify_fix → lint_synth
     1            2          3            4

Cocotb-First Integration Simulation

Stage 3 (verify_fix) uses cocotb (Python co-simulation) as the primary simulation path when available: - cocotb's await RisingEdge(dut.clk) fires via VPI callback AFTER the NBA region, eliminating all Verilog TB-DUT race conditions - Per-cycle internal register comparison against golden model trace - Cycle-level timing contract assertions (registered output stability, pipeline delay) - Falls back to Verilog $display-based testbenches when cocotb is unavailable

Simulation passes but pipeline reports FAIL

The sim hook uses strict 3-layer verification: (1) sim.log must be non-empty, (2) no [FAIL] or FAILED: lines, (3) must contain ALL TESTS PASSED. If your testbench prints [FAIL] in passing messages (e.g., "checking FAIL case"), use a different format to avoid triggering Layer 2.

Troubleshooting