VeriFlow-CC 是 AI Skill Hub 本期精选Agent工作流之一。综合评分 7.5 分，整体质量较高。我们推荐使用将其纳入你的 AI 工具库，帮助提升工作效率。
VeriFlow-CC是基于Claude Code的开源AI工作流，用于自动化芯片设计流程。它通过智能化的设计和优化，提高芯片设计的效率和质量。
VeriFlow-CC 是一套完整的 AI Agent 自动化工作流方案。通过可视化的节点编排，将复杂的多步骤任务拆解为清晰的自动化流程，实现全程无人值守的智能处理。支持与数百种外部服务和 API 无缝集成，适合构建数据处理管线、业务自动化和 AI 辅助决策系统。
VeriFlow-CC是基于Claude Code的开源AI工作流，用于自动化芯片设计流程。它通过智能化的设计和优化，提高芯片设计的效率和质量。
VeriFlow-CC 是一套完整的 AI Agent 自动化工作流方案。通过可视化的节点编排，将复杂的多步骤任务拆解为清晰的自动化流程，实现全程无人值守的智能处理。支持与数百种外部服务和 API 无缝集成，适合构建数据处理管线、业务自动化和 AI 辅助决策系统。
# 方式一：pip 安装（推荐）
pip install veriflow-cc
# 方式二：虚拟环境安装（推荐生产环境）
python -m venv .venv
source .venv/bin/activate # Windows: .venv\Scripts\activate
pip install veriflow-cc
# 方式三：从源码安装（获取最新功能）
git clone https://github.com/bjwanneng/veriflow-cc
cd veriflow-cc
pip install -e .
# 验证安装
python -c "import veriflow_cc; print('安装成功')"
# 命令行使用
veriflow-cc --help
# 基本用法
veriflow-cc input_file -o output_file
# Python 代码中调用
import veriflow_cc
# 示例
result = veriflow_cc.process("input")
print(result)
# veriflow-cc 配置文件示例（config.yml） app: name: "veriflow-cc" debug: false log_level: "INFO" # 运行时指定配置文件 veriflow-cc --config config.yml # 或通过环境变量配置 export VERIFLOW_CC_API_KEY="your-key" export VERIFLOW_CC_OUTPUT_DIR="./output"
Claude Code-driven RTL design pipeline — zero Python dependencies, Claude Code main session is the driver.
iverilog / vvp (optional, for lint/sim stages)yosys (optional, for synth stage)No pip install required.
git clone https://github.com/bjwanneng/veriflow-cc.git
cd veriflow-cc
python install.pyInstalls to ~/.claude/: - skills/vf-rtl/SKILL.md — Pipeline orchestration skill - skills/vf-rtl/state.py — State management - skills/vf-rtl/vcd2table.py — VCD waveform analysis - skills/vf-rtl/coding_style.md — Verilog coding style rules - skills/vf-rtl/cocotb_runner.py — Cocotb simulation runner - skills/vf-rtl/iverilog_runner.py — Pure-Verilog simulation runner - skills/vf-rtl/timing_contract_checker.py — Timing contract validator - skills/vf-rtl/benchmark_runner.py — Batch evaluation & reporting - skills/vf-rtl/bug_pattern_match.py — Automated divergence pattern matching - skills/vf-rtl/corner_case_generator.py — Boundary test vector generation - skills/vf-rtl/formal_property_gen.py — Assertion generation from timing contracts - skills/vf-rtl/design_graph.py — Module connectivity graph analysis - skills/vf-rtl/cross_verify.py — Dual-RTL equivalence comparison - skills/vf-rtl/knowledge_base.py — Cross-project bug pattern learning - agents/vf-coder.md — RTL code generation sub-agent - agents/vf-spec-golden.md — Spec + golden model generation sub-agent - agents/vf-tb-gen.md — Testbench generation sub-agent - agents/vf-linter.md — Lint sub-agent - agents/vf-synthesizer.md — Synthesis sub-agent
Uninstall: python install.py --uninstall
python install.py --uninstallEDA tool paths (iverilog, vvp, yosys) are discovered once in Step 0 and saved to .veriflow/eda_env.sh. Every subsequent EDA command sources this file, avoiding the "PATH doesn't persist between Bash calls" issue. eda_env.sh also exports PYTHONPATH pointing at the installed skill directory, so helper scripts can import state.py without per-call PYTHONPATH prefixes.
spec.json port definitions are locked after Stage 1. Port semantic fields enforce consistent interpretation across all stages: - reset_polarity: "active_high" only (reset ports must declare this) - handshake: "hold_until_ack" | "single_cycle" | "pulse" (valid ports must declare this) - ack_port: name of the associated ack input (required for hold_until_ack)
Strict sequential execution, no skipping:
spec_golden → codegen → verify_fix → lint_synth
1 2 3 4| Stage | Type | Input | Output |
|---|---|---|---|
| spec_golden | LLM (vf-spec-golden) | requirement.md, constraints.md, design_intent.md, context/ | spec.json + golden_model.py |
| codegen | vf-coder sub-agent (AI assembly per module, parallel) | spec.json, golden_model.py, coding_style.md | rtl/*.v |
| verify_fix | EDA (iverilog+vvp or cocotb) + error recovery | rtl/*.v, tb/*.v, golden_model.py | logs/sim.log, VCD waveform analysis, expected_trace_*.md |
| lint_synth | EDA (iverilog + yosys, parallel) | rtl/*.v | logs/lint.log + synth_report.txt |
Stage 3 (verify_fix) uses cocotb (Python co-simulation) as the primary simulation path when available: - cocotb's await RisingEdge(dut.clk) fires via VPI callback AFTER the NBA region, eliminating all Verilog TB-DUT race conditions - Per-cycle internal register comparison against golden model trace - Cycle-level timing contract assertions (registered output stability, pipeline delay) - Falls back to Verilog $display-based testbenches when cocotb is unavailable
The sim hook uses strict 3-layer verification: (1) sim.log must be non-empty, (2) no [FAIL] or FAILED: lines, (3) must contain ALL TESTS PASSED. If your testbench prints [FAIL] in passing messages (e.g., "checking FAIL case"), use a different format to avoid triggering Layer 2.
VeriFlow-CC是一个有潜力的开源AI工作流，通过Claude Code的智能化设计和优化，提高了芯片设计的效率和质量。但是，需要进一步的开发和测试来确保其稳定性和可靠性。
该工具未明确声明开源协议，商业使用前请联系原作者确认授权范围，避免侵权风险。
AI Skill Hub 为第三方内容聚合平台，本页面信息基于公开数据整理，不对工具功能和质量作任何法律背书。
建议在沙箱或测试环境中充分验证后，再部署至生产环境，并做好必要的安全评估。
经综合评估，VeriFlow-CC 在Agent工作流赛道中表现稳健，质量良好。如果你已有明确的使用需求，可以直接上手体验；如果还在评估阶段，建议对比同类工具后再做决策。
| 原始名称 | veriflow-cc |
| 原始描述 | 开源AI工作流：VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat fr。⭐18 · Python |
| Topics | workflowai-agentschip-designclaude-code-skillclaude-code-skills |
| GitHub | https://github.com/bjwanneng/veriflow-cc |
| 语言 | Python |
收录时间：2026-05-25 · 更新时间：2026-05-26 · License：未公布 · AI Skill Hub 不对第三方内容的准确性作法律背书。
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