---
tags: [Language, Verilog]
---

# Verilog

## Getting Started

- [FPGA Workflow](./workflow.md) - Complete FPGA development process from project creation to bitstream generation
- [Timing Constraints](./timing.md) - Circuit timing theory including setup/hold times and clock skew

## Core Concepts

- [Module](./module.md) - Module structure, ports, instantiation, functions, and tasks
- [Data Types](./types.md) - Constants, vectors, arrays, numbers, registers, nets, and preprocessor directives

## Modeling Styles

- [Gate](./gate.md) - Primitive gates, gate instantiation, and generate statements
- [Dataflow](./dataflow.md) - Continuous assignments and operators
- [Behavior](./behavior.md) - Procedural blocks, control structures, and delay specifications

## Advanced Topics

- [State Machine](./state-machine.md) - Finite state machines and arithmetic state machines
- [SystemVerilog](./systemverilog.md) - SystemVerilog enhancements including enums, structs, interfaces, and OOP

## Platform

- [Xilinx U280](./xilinx.md) - Xilinx U280 FPGA board specific toolchain and host application
- [AXI Protocol](./axi.md) - AXI bus protocol channels and burst transfers

## Components

- [Hardware Components](./components.md) - Hardware component implementations including multipliers, ALU, memory, etc.

## Best Practices

- [Best Practices](./best-practices.md) - Coding guidelines, synthesizable constructs, and parameter usage
