# Formal Verification Skill

Formal property verification and model checking skill for FPGA designs.

## Purpose

This skill provides formal expertise, enabling:
- Exhaustive property verification
- Bug detection without simulation
- Protocol compliance checking
- Coverage-hole identification

## Key Features

- Formal property writing
- Tool constraint configuration
- Counterexample analysis
- Bounded model checking
- Cover and assume directives
- Formal-simulation integration
- JasperGold and VC Formal support

## Integration

Used primarily with:
- SVA Development Process
- CDC Design Process
- Constrained Random Verification Process

## Related

- SK-017 in skills-agents-backlog.md
- Verification Expert Agent (AG-003)
- CDC Expert Agent (AG-004)
