# UVM Methodology Skill

Deep expertise in Universal Verification Methodology (IEEE 1800.2) for comprehensive FPGA verification.

## Purpose

This skill provides UVM expertise, enabling:
- Systematic verification environments
- Constrained random testing
- Functional coverage closure
- Reusable verification IP

## Key Features

- UVM agent architecture generation
- Environment and scoreboard creation
- Sequence and virtual sequence implementation
- Factory and config_db configuration
- Register abstraction layer (RAL)
- Coverage-driven verification

## Integration

Used primarily with:
- UVM Testbench Process
- Constrained Random Verification Process
- Testbench Development Process

## Related

- SK-007 in skills-agents-backlog.md
- Verification Expert Agent (AG-003)
